1. Field
Embodiments of the present invention relate to a semiconductor device wherein an electrode of a semiconductor chip mounted on an insulating substrate inside a semiconductor device is electrically connected via a conductive post to a printed substrate sealed inside the semiconductor device.
2. Discussion of the Background
A semiconductor device in which is mounted a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) or power-FET (Field Effect Transistor) is used in power conversion devices, uninterruptible power supply devices, machine tools, industrial robots, and the like. A semiconductor device having copper blocks disposed on the front and back of an insulating substrate with a conductive pattern, an IGBT chip and diode chip disposed on the front side copper block, and the IGBT chip and diode chip and the printed substrate are connected by a plurality of implant pins, has been proposed as the semiconductor device (for example, refer to International Publication 2011/083737).
Also, a semiconductor device including at least one semiconductor element (semiconductor chip) joined onto a metal foil formed on an insulating plate, a printed substrate disposed opposing the semiconductor element (semiconductor chip), and a plurality of post electrodes that electrically connect at least one metal foil formed on first and second main surfaces of the printed substrate and at least one main electrode of the semiconductor element (semiconductor chip), has been proposed as another semiconductor device (for example, refer to Japanese Publication JP-A-2009-64852). The semiconductor device described in Japanese Publication JP-A-2009-64852 is a type of semiconductor module such that a main electrode of a semiconductor chip is electrically connected by a plurality of post electrodes (conductive posts), as shown in FIG. 12 and FIG. 13. A semiconductor module 201 has a structure such that an insulating substrate 202 and an implant printed substrate 203 (hereafter called simply a printed substrate) caused to oppose the insulating substrate 202 are integrated by sealing with an under filling material, resin material, or the like, 204. A plurality of semiconductor chips 205 are mounted on the insulating substrate 202.
Furthermore, the semiconductor module 201 is packaged with a resin case (not shown), and functions as, for example, a general-purpose IGBT module. The insulating substrate 202 includes an insulating plate 206, a metal foil 207 formed using a DCB (Direct Copper Bonding) method on the lower surface of the insulating plate 206, and a plurality of metal foils 208 formed, also using a DCB method, on the upper surface of the insulating plate 206. The semiconductor chips 205 are joined onto the metal foils 208 across a lead-free solder layer 209 of a tin (Sn)-silver (Ag) series.
Also, the printed substrate 203 is of a multilayer structure wherein, for example, a resin layer 213 is disposed in a central portion, metal foils 214 are formed by patterning on the upper surface and lower surface of the resin layer 213, and the metal foils 214 are covered by protective layers 215. A plurality of through holes 210 are provided in the printed substrate 203. A thin, tubular plating layer (not shown) that electrically connects the upper surface and lower surface metal foils 214 is provided inside the through holes 210, and cylindrical post electrodes (conductive posts) 211 are implanted across the tubular plating.
Furthermore, as shown in FIG. 12, the semiconductor chip 205 includes an emitter electrode pad 205a, disposed over a comparatively large area in a central portion of the upper surface, and a gate electrode pad 205b with a comparatively small area formed between the emitter electrode pad 205a and a front edge portion. Further, two rows of, for example, five each of the post electrodes (conductive posts) 211 are joined in parallel to the emitter electrode pad 205a. Also, one post electrode (conductive post) 212 is joined to the gate electrode pad 205b. Also, as a large amount of heat is generated in a large current semiconductor chip mounted in a semiconductor device, various measures are taken in order to equalize the semiconductor chip temperature distribution. For example, there has been proposed a semiconductor device that is a large current semiconductor device affected by local distribution of the resistance of an upper electrode layer, wherein temperature rise distribution is fixed depending on the planar distribution conditions of a plurality of connection portions inside the upper electrode layer, and semiconductor chip temperature distribution is equalized by the connection portions being disposed in a zigzag form (for example, refer to Japanese Publication JP-A-2006-66704).
Also, there has been proposed a semiconductor device wherein, by an electrode member such that copper posts are formed in a plurality of through holes provided in a ceramic support body being joined by solder to a surface side on which an IGBT emitter electrode is formed, and the plurality of copper posts being joined by solder to the emitter electrode, heat generated in the IGBT moves to the electrode member and is released and, even when there is a difference in thermal expansion coefficient between the material configuring the IGBT and the copper, the stress exerted on the solder joint interface is reduced, thus keeping distortion small, and reducing the occurrence of cracks (for example, refer to Japanese Publication JP-A-2006-237429). The semiconductor device described in Japanese Publication JP-A-2006-237429 is such that the sectional area (diameter) of the copper posts in a central portion of the support body is greater than the diameter of the copper posts in a peripheral portion, the copper posts with the greater sectional area are formed in the central portion, which has low thermal stress, and a large number of the copper posts with the smaller sectional area are disposed in the peripheral portion, which has high thermal stress. Because of this, the solder layer is thickened, and the occurrence of cracks at the solder joint interface is suppressed.
Further, there has also been proposed a semiconductor device such that temperature rise in the central portion of a surface electrode with inferior heat releasing properties is suppressed using a method whereby the combined resistance reaching from a semiconductor element to the central portion of the surface electrode and, via a metal wire, to an external electrode is set to be larger than the combined resistance reaching from the semiconductor element to a peripheral portion of the surface electrode and, via a metal wire, to an external electrode, or by a metal wire being joined only to the peripheral portion of the surface electrode, or the like, in order to suppress temperature rise in the central portion of the surface electrode with inferior heat releasing properties, (for example, refer to Japanese Publication JP-A-2003-188378). Furthermore, there has also been proposed a semiconductor device such that a power semiconductor device such as an IGBT is a semiconductor device that, in order to equalize temperature distribution due to heat generation on a chip surface, includes electrodes on the front and back chip surfaces of a semiconductor chip such as an IGBT, wherein current flows between the electrode on one chip surface and the electrode on the other chip surface when an on-state operation is carried out, a plurality of wires are connected with a non-uniform disposition distribution to the electrode on the one chip surface of the semiconductor chip and, based on a predetermined reference, the number of wires connected to a peripheral portion of the one chip surface is greater than the number of wires connected to a central portion of the one chip surface (for example, refer to Japanese Publication JP-A-2008-186957).